In many applications, data is sent in a serial manner from a transmitting device to a receiving device. In order to properly receive the serial data, the receiving device typically needs timing information about when each datum, symbol or bit of the serial data is to be received. In some cases, the data is transmitted with an associated clock signal which provides the timing information needed for the receiving device to properly receive the data. However, in other cases, the serial data is delivered to the receiving device without a clock signal. In such cases, the receiving device needs to ascertain the timing information from the received data. An example of such a case is discussed as follows.
FIG. 1 illustrates a block diagram of a serializer/deserializer (Ser/Des) communication system 100. The Ser/Des communication system 100 includes a serializer 102 communicatively coupled to a deserializer 104. The serializer 102 typically includes a plurality of inputs to receive time-sensitive parallel data. The serializer 102 then multiplexes the parallel data to generate serial data. The serializer 102 then sends the serial data to the deserializer 104, which demultiplexes the serial data to recover the original parallel data.
As previously discussed, the serial data may not be sent with an associated clock signal which the deserializer 104 may use to properly receive the serial data. In such a case, the receiving device, in this case the deserializer 104, employs a clock recovery circuit that generates a clock signal timely associated with a special training pattern in the serial data so that the receiving device can properly extract the data. Often, the clock recovery circuit is configured as a phase locked loop (PLL) which generates a clock signal timely associated with the received serial data. An example of a clock recovery circuit is discussed as follows.
FIG. 2 illustrates a block diagram of an exemplary clock recovery circuit 200 that may be employed in the deserializer 104 of the Ser/Des communication system 100. The clock recovery circuit 200 includes a frequency detector 202, a charge pump 204, a low pass loop filter 206, a voltage controlled oscillator (VCO) 208, and a frequency divider 210. The frequency detector 202 receives the incoming serial data and the output of the frequency divider 210. The frequency detector 202 compares the frequencies of the two signals, and causes either a PD_UP or PD_DN control signal to go high in response to the error in frequency between the serial data and the output of the frequency divider 210. The frequency detector 202 causes either the PD_UP or PD_DN control signal to go high in order to minimize the error in frequency between the serial data and the output of the frequency divider 210.
If the frequency detector 202 causes the PD_UP signal to go high, the charge pump 204 generates a positive current going into the low pass loop filter 206. The low pass loop filter 206 integrates the current from the charge pump 204 to increase the control voltage VCON for the VCO 208. This, in turn, causes the frequency of the clock signal generated by the VCO 208 to increase, which also causes the frequency of the output of the frequency divider 210 to increase. On the other hand, if the frequency detector 202 causes the PD_DN signal to go high, the charge pump 204 generates a negative current that removes charges from the loop filter 206. This has the effect of lowering the VCO control voltage VCON. This, in turn, causes the frequency of the clock signal generated by the VCO 208 to decrease, which also causes the frequency of the output of the frequency divider 210 to decrease.
Once the clock recovery circuit 200 recovers the clock signal, the mode of the circuit is changed to a data recovery. As discussed in more detail below, in data recovery mode, the phase of the clock signal generated by the VCO 208 is modified to ensure a proper recovery of the incoming serial data. If the incoming serial data ceases, there is no more timing information being received to keep the frequency of the clock signal in synchronous with the incoming data. For instance, the data may discontinue during a vertical or horizontal blanking period of a video signal. Due to current leakage at the VCO control node, which may be caused by reverse junction current leakage, the VCO control voltage VCON may tend to drift. This causes the frequency of the VCO clock signal to drift. The drift may be so substantial that when data is received again, the data recovery operation may not work properly, and a whole new process of re-acquiring the clock needs to be implemented.